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SP8480* Monolithic, 12-Bit Data Acquisition System
s Complete Monolithic 8-Channel, 12-Bit DAS s 100kHz Throughput s 16-Bit Microprocessor Bus Interface s MUX Inputs Overvoltage Protected s Parallel 8/4-Bit Nibble Output s Tri-State Latched Output s No Missing Codes to 12-Bits s 28-pin SOIC and PDIP package s 200mW Max Power Dissipation (140mw Typ.)
*Formerly part of the SP410 Series.
DESCRIPTION... The SP8480 Series are complete monolithic data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter in 28-pin plastic DIP or SOIC packages. Linearity errors of 0.5 and 1.0 LSB, and Differential Non-linearity to 12-bits are guaranteed, with no missing codes over temperature. Multiplexer settling plus acquisition time is 1.9s maximum; A/D conversion time is 8.1s maximum.
MULTIPLEXER
12-BIT A/D CONVERTER
MUX DECODE
REFERENCE
CONTROL LOGIC
CLOCK
8-BIT/4-BIT NIBBLE OUTPUT
289
ABSOLUTE MAXIMUM RATINGS
V to Common Ground ............................................... 0V to +16.5V V to Common Ground .................................................. 0V to +7V Analog Common to Digital Common Ground ............... -0.5V to +1V Digital Inputs to Common Ground ...................... -0.5V to V +0.5V Digital Outputs to Common Ground ................... -0.5V to V +0.5V Multiplexer Analog Inputs ...................................... -16.5V to +31.5V Gain and Offset Adjustment ................................. -0.5V to V +0.5V Analog Input Maximum Current ............................................. 25mA Temperature with Bias Applied ............................. -55C to +125C Storage Temperature ............................................ -65C to +150C Lead Temperature, Soldering .................................... 300C, 10sec
CC LOGIC LOGIC LOGIC CC
SPECIFICATIONS
(TA= 25C and nominal supply voltages unless otherwise noted)
MIN. ANALOG INPUTS Input Voltage Range Multiplexer Inputs Configuration Input Impedance ON Channel OFF Channel Input Bias Current Per Channel Crosstalk OFF to ON Channel
TYP. 0 to +5
MAX.
UNIT V
CONDITIONS
8 Single-ended 109 1010 10 250 -90 -80 -70 nA nA dB dB dB Bits LSB LSB LSB LSB LSB %FSR Parallel with 30pF Parallel with 5pF 25C -55C to +125C 10kHz, 0V to +5Vpk-to-pk 50kHz, 0V to +5Vpk-to-pk 100kHz, 0V to +5Vpk-to-pk
ACCURACY Resolution 12 Linearity Error -K, -B 0.5 -J, -A 1 Differential Non-Linearity -K, -B 1 -J, -A 2 Offset Error 2 Gain Error 0.3 No Missing Codes -K, -B Guaranteed TRANSFER CHARACTERISTICS Throughput Rate 100 MUX Settling/Acquisition 1.9 A/D Conversion 8.1 STABILITY Linearity 0.5 2.5 Offset 5 25 Gain 10 50 DIGITAL INPUTS Capacitance 5 Logic Levels VIH +2.4 +5.5 VIL -0.5 +0.8 IIH 5 IIL 5
Adjustable to zero Adjustable to zero
kHz s s ppm/C ppm/C ppm/C pF V V A A
290
SPECIFICATIONS
(TA= 25C and nominal supply voltages unless otherwise noted)
MIN. DIGITAL OUTPUTS Capacitance Logic Levels VOH VOL Leakage Current Data Output POWER REQUIREMENTS VLOGIC ILOGIC VCC ICC Power Dissipation ENVIRONMENTAL Operating Temperature Commercial; -J, -K Industrial; -A, -B Storage Temperature
TYP. 5
MAX.
UNIT pF
CONDITIONS
+2.4 40 Offset Binary +4.5 0.8 +11.4 9 140 +0.4
V V A
I OH 500A I OL 1.6mA High impedance, data bits only
+5.5 4 +16.5 12 200
V mA V mA mW
0 -40 -65
+70 +85 +150
C C C
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PIN FUNCTION... A0 -- Device Address -- Logic low enables 8 MSB read; logic high enables 4 LSB read STATUS -- Identifies valid data output; goes to logic high during conversion; goes to logic low when conversion is completed and data is valid R/C -- Read/Convert -- Initiates conversion on the high-to-low transition; logic low disconnects data bus; logic high initiates read
DB8/DB0 (LSB)
CE -- Chip Enable -- Logic low disables read or convert; logic high enables read or convert MA0, MA1, MA2 -- MUX Address 0, 1 & 2 -- Selects analog input channels CH0 through CH7 DB0 through DB11 -- Data Outputs -- Logic high is binary true; logic low binary false CONTROL TRUTH TABLE
A
O
R/C H ->L 1 1
OPERATION Start Conversion Enable 8 MSBs Enable 4 LSBs
DIG. GND.
DB11/DB3
DB10/DB2
X 0 1
DB9/DB1
STATUS
VLOGIC
MA2
MA1
28 27 26 25 24 23 22 21 20 19 18 17 16 15
MA0
DB7
DB6
DB5
DB4
MULTIPLEXER TRUTH TABLE
CONTROL LOGIC
REF 12-BIT ADC
CLOCK
MA2 0 0 0 0 1 1 1 1
MA1 MA0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
OPERATION CHO Selected CH1 Selected CH2 Selected CH3 Selected CH4 Selected CH5 Selected CH6 Selected CH7 Selected
DECODE
8-CHANNEL MULTIPLEXER 4
OFFSET ADJ.
1
A0
2
R/C
3
VCC
5
GAIN ADJ.
6
ANA. GND.
7
ANA. IN. CH0
8
ANA. IN. CH1
9 10 11 12 13 14
ANA. IN. CH2 ANA. IN. CH3 ANA. IN. CH4 ANA. IN. CH5 ANA. IN. CH6 ANA. IN. CH7
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FEATURES... The SP8480 Series are complete data acquisition systems, featuring 8-channel multiplexer, internal reference and 12-bit sampling A/D converter implemented as a single monolithic IC. The analog multiplexer accepts 0V to +5V unipolar full scale inputs. Output data is formatted as an 8-bit/4-bit nibble. Linearity errors of 0.5 and 1.0 LSB, and Differential Non-linearity to 12-bits is guaranteed, with no missing codes over temperature. Channel-to-channel crosstalk is typically -85dB. Multiplexer settling plus acquisition time is 1.9s maximum; A/D conversion time is 8.1s maximum. Versions of the SP8480 are available in 28-pin plastic DIP, ceramic DIP or SOIC packages. Operating temperature ranges are 0C to +70C commercial and -40C to +85C industrial.
The SAR, timed by the clock, sequences through the conversion cycle and returns an end-of- convert flag to the control section of the ADC. The clock is then disabled by the control section, which puts the STATUS output line low. The control section is enabled to allow the data to be read by external command (R/C). Multiplexer Control and Inputs On the SP8480 the multiplexer is independent of any other control line. The address line latches MA , MA and MA are hard-wired in an enabled mode in the SP8480, and are therefore transparent. Data setup time for these inputs is 50ns. If a device is required with additional MUX control, please refer to the Sipex SP8481 DAS. Since the latches are enabled, MUX channel select data need not be held by the bus for a minimum period of 3.0s after the conversion has been initiated. This is the time required for the MUX and Sample and Hold to settle. However it is advisable that the MUX not be changed at all during the full 10s conversion time due to capacitive coupling effects of digital edges through the silicon.
0 1 2
CIRCUIT OPERATION... The SP8480 is a complete 8-channel data acquisition systems (DAS), with on-board multiplexer, voltage reference, sample-and-hold, clock and tri-state outputs. The digital control architecture is very similar to the industry-standard 574-type A/D, and uses identical control lines and digital states. The multiplexer for the SP8480 is identical in operation to many discrete devices available today, except that it has been integrated into the single-chip DAS. The appropriate channel is selected using the MUX address lines MA0, MA1, and MA2 per the truth table. The selected analog input is fed through to the ADC. The input impedance into any MUX channel will be on the order to 109 ohms, since it is connected to the integral sampling structure of the capacitor DAC. Crosstalk is kept to -85dB at 0V to 5V over an input frequency range of 10kHz to 50kHz.
p-p
The SP8480 multiplexer inputs have been designed to allow substantial overvoltage conditions to occur without any damage. The inputs are diode-clamped and further protected with a 200 series resistor. As a result, momentary (10 seconds) input voltages can be as low as -16.5V or as high as +31.5V with no change or degradation in multiplexer performance or crosstalk. This feature allows the output voltage of an externally connected op amp to swing to 15V supply levels with no multiplexer damage. Complicated power-up sequencing is not required to protect the SP8480. The multiplexer inputs may be damaged, however, if the inputs are allowed to either source or sink greater than 100mA. Initiating A Conversion Please refer to Figure 4. The SP8480 was designed to require a minimum of control to perform a 12-bit conversion. The control input used is R/C which tri-states the outputs and starts the conversion when low. The STATUS line indicates when a conversion is in process and when it is complete. The A control input is used to
0
When the internal control section of the SP8480 initiates a conversion command the internal clock is enabled, and the successive approximation register (SAR) is reset to all zeros. Once the conversion has been started it cannot be stopped or restarted. Data is not available at the output buffers until the conversion has been completed.
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latch the 8 MSB's and 4 LSB's of output data on the 8-bit wide output data bus. The conversion cycle is started when R/C is brought low and must be held low for a minimum of 50ns. The R/C signal will also cause the output latches to be in a tri-state mode when low. Approximately 200ns after R/C is low, STATUS will change from low to high. This output signal will stay high while the SP8480 is performing a conversion. Valid data will be latched to the output bus, through internal control, 500ns prior to the STATUS line transitioning from a high to low. Reading the Data Please refer to Figure 5. To read data from the SP8480, the R/C and A control lines are used. R/C must be high a minimum of 50ns prior to reading the data to allow time for the output latches to come out of the high impedance tri-state mode. A is used to access the data. The first 8 MSBs will be on pins 26 through 19, with pin 26 being the MSB. The remaining 4 LSBs will be on pins 23 through 26 with pin 23 being the LSB. When A is switched from one state to the next, there is a 50ns output latch propagation delay between the MSBs and LSBs being present on the output pins.
0 0 0
+15V
SP8480
GAIN ADJUST 5
Center pot for zero correction
125K
10K
0.3% Trim Range 19K
Figure 2. Gain Adjust
Offset Adjustment The offset adjustment must be completed first. Please refer to Figure 1. Apply an input voltage of 0.5LSB or 610V to any multiplexer input. Adjust the offset potentiometer so that the output code fluctuates evenly between 000...000 and 000...001. It is only necessary to observe the lower eight LSB's during this procedure. Gain Adjustment With the offset adjusted, the gain error can now be trimmed to zero (see Figure 2). The ideal input voltage corresponding to 1.5 LSB's below the nominal full scale input value, or +4.988V, is applied to any multiplexer input. The gain potentiometer is adjusted so that the output code alternates evenly between 111...111 and 111...110. Again, only the lower eight LSB's need be observed during this procedure. With the above adjustment made, the converter is now calibrated.
CALIBRATION The calibration procedure for the SP8480 consists of adjusting the most negative input voltage (0V) to the ideal output code for offset adjustment, and then adjusting the most positive input voltage (5.0V) to its ideal output code for gain adjustment.
+15V
100K
SP8480
OFFSET ADJUST 4 -1.5mV to +3mV 5K
Figure 1. Offset Adjust
294
tMDH tMDS MA0 - MA2 tHRL R/C tDS STATUS tHDR DB11 - DB0 DATA VALID tC tHS DATA VALID
LOW PULSE FOR R/C DYNAMIC CHARACTERISTICS
VCC = +15V; VLOGIC = +5V; T A = 25C
PARAMETER tHRL Low R/C Pulse Width tDS tHDR tHS tMDS tMDH Status Delay from R/C Data Valid after R/C Low Status Delay after Data Valid MUX Data Setup MUX Data Valid
MIN 50 25 500 50 3
TYP
MAX 200
UNIT ns ns ns ns ns
CONDITIONS
10
s
Figure 3. Low Pulse for R/C Timing
295
tSRC R/C
tHRC STATUS tDSC DB11 - DB0 tHDR HIGH IMPEDANCE tC
CONVERT MODE DYNAMIC CHARACTERISTICS
V = +15V; V
CC LOGIC
= +5V; T = 25C
A
PARAMETER t SRC t HRC t DSC R/C to CE Setup R/C Low during CE High Status Delay from CE
MIN 50 50
TYP
MAX
UNIT ns ns
CONDITIONS
200
ns
Figure 4. Convert Mode Timing
296
R/C tHRH tDS tC tDDR DB11 - DB0 HIGH IMPEDANCE DATA VALID DB11-DB4 A0 tHDR DATA VALID DB3-DB0, 0000 HIGH IMPEDANCE
STATUS
tADS
READ MODE DYNAMIC CHARACTERISTICS
VCC = +15V; VLOGIC = +5V; T A = 25C
PARAMETER tHRH Read Pulse Width tDS tC tDDR tHDR tADS Status Delay from R/C Conversion Time Data Bits Out of High Z Delay Data Valid after R/C Low A0 High or Low to Data Setup
MIN 150
TYP
MAX 200 10
UNIT ns ns s ns ns ns
CONDITIONS
0 25
100 50
Figure 5. Read Mode Timing
297
Figure 6. FFT; 6kHz 5V (0dB) Full Scale Input; FS=10kHz
Figure 7. FFT; 12kHz 5V (0dB) Full Scale Input; FS=10kHz
Figure 8. FFT; 24kHz 5V (0dB) Full Scale Input; FS=10kHz
Figure 9. FFT; 48kHz 5V (0dB) Full Scale Input; FS=10kHz
Figure 10. FFT; 48kHz 1V (-14dB) Input; FS=10kHz
298
ORDERING INFORMATION
12-Bit Data Acquisition System with 12-Bit Parallel Data Output: Commercial (0C to +70C): Non-Linearity Package SP8480JP .................................................................................... 1.0LSB INL ................................................................... 28-pin, 0.6" Plastic DIP SP8480KP ................................................................................... 0.5LSB INL ................................................................... 28-pin, 0.6" Plastic DIP SP8480JS .................................................................................... 1.0LSB INL ............................................................................ 28-pin, 0.3" SOIC SP8480KS ................................................................................... 0.5LSB INL ............................................................................ 28-pin, 0.3" SOIC Industrial (-40C to +85C): Non-Linearity Package SP8480AP ................................................................................... 1.0LSB INL ................................................................... 28-pin, 0.6" Plastic DIP SP8480BP ................................................................................... 0.5LSB INL ................................................................... 28-pin, 0.6" Plastic DIP SP8480AS ................................................................................... 1.0LSB INL ............................................................................ 28-pin, 0.3" SOIC SP8480BS ................................................................................... 0.5LSB INL ............................................................................ 28-pin, 0.3" SOIC
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